1 /* Converted to D from papiStdEventDefs.h by htod */
2 module lib.papiStdEventDefs;
3 extern(C):
4 @nogc:
5 /* Converted to D from papiStdEventDefs.h by htod */
6 
7 
8 /* file: papiStdEventDefs.h
9 
10 The following is a list of hardware events deemed relevant and useful
11 in tuning application performance. These events have identical
12 assignments in the header files on different platforms however they
13 may differ in their actual semantics. In addition, all of these events
14 are not guaranteed to be present on all platforms.  Please check your
15 platform's documentation carefully.
16 
17 */
18 //C     #ifndef _PAPISTDEVENTDEFS
19 //C     #define _PAPISTDEVENTDEFS
20 
21 /*
22    Masks to indicate the event is a preset- the presets will have 
23    the high bit set to one, as the vendors probably won't use the 
24    higher numbers for the native events 
25    This causes a problem for signed ints on 64 bit systems, since the
26    'high bit' is no longer the high bit. An alternative is to AND
27    with PAPI_PRESET_AND_MASK) instead of XOR with PAPI_PRESET_MASK to isolate
28    the event bits.
29    Native events for a specific platform can be defined by setting
30    the next-highest bit. This gives PAPI a standardized way of 
31    differentiating native events from preset events for query
32    functions, etc.
33 */
34 
35 const int PAPI_PRESET_MASK    = 0x80000000;
36 const int  PAPI_NATIVE_MASK   =  (0x40000000);
37 const int PAPI_UE_MASK		= (0xC0000000);
38 
39 
40 const PAPI_PRESET_AND_MASK = 0x7FFFFFFF;
41 //C     #define PAPI_UE_AND_MASK     0x3FFFFFFF
42 const PAPI_NATIVE_AND_MASK = 0xBFFFFFFF;
43 
44 const PAPI_UE_AND_MASK = 0x3FFFFFFF;
45 //C     #define PAPI_MAX_PRESET_EVENTS 128		/*The maxmimum number of preset events */
46 //C     #define PAPI_MAX_USER_EVENTS 50			/*The maxmimum number of user defined events */
47 const PAPI_MAX_PRESET_EVENTS = 128;
48 //C     #define USER_EVENT_OPERATION_LEN 512	/*The maximum length of the operation string for user defined events */
49 const PAPI_MAX_USER_EVENTS = 50;
50 
51 const USER_EVENT_OPERATION_LEN = 512;
52 /*
53    NOTE: The table below defines each entry in terms of a mask and an integer.
54    The integers MUST be in consecutive order with no gaps.
55    If an event is removed or added, all following events MUST be renumbered.
56    One way to fix this would be to recast each #define in terms of the preceeding
57    one instead of an absolute number. e.g.:
58      #define PAPI_L1_ICM  (PAPI_L1_DCM + 1)
59    That way inserting or deleting events would only affect the definition of one
60    other event.
61 */
62 
63 //C     enum
64 //C     {
65 //C     	PAPI_L1_DCM_idx = 0,			   /*Level 1 data cache misses */
66 //C     	PAPI_L1_ICM_idx,		 /*Level 1 instruction cache misses */
67 //C     	PAPI_L2_DCM_idx,		 /*Level 2 data cache misses */
68 //C     	PAPI_L2_ICM_idx,		 /*Level 2 instruction cache misses */
69 //C     	PAPI_L3_DCM_idx,		 /*Level 3 data cache misses */
70 //C     	PAPI_L3_ICM_idx,		 /*Level 3 instruction cache misses */
71 //C     	PAPI_L1_TCM_idx,		 /*Level 1 total cache misses */
72 //C     	PAPI_L2_TCM_idx,		 /*Level 2 total cache misses */
73 //C     	PAPI_L3_TCM_idx,		 /*Level 3 total cache misses */
74 //C     	PAPI_CA_SNP_idx,		 /*Snoops */
75 //C     	PAPI_CA_SHR_idx,		 /*Request for shared cache line (SMP) */
76 //C     	PAPI_CA_CLN_idx,		 /*Request for clean cache line (SMP) */
77 //C     	PAPI_CA_INV_idx,		 /*Request for cache line Invalidation (SMP) */
78 //C     	PAPI_CA_ITV_idx,		 /*Request for cache line Intervention (SMP) */
79 //C     	PAPI_L3_LDM_idx,		 /*Level 3 load misses */
80 //C     	PAPI_L3_STM_idx,		 /*Level 3 store misses */
81 /* 0x10 */
82 //C     	PAPI_BRU_IDL_idx,		 /*Cycles branch units are idle */
83 //C     	PAPI_FXU_IDL_idx,		 /*Cycles integer units are idle */
84 //C     	PAPI_FPU_IDL_idx,		 /*Cycles floating point units are idle */
85 //C     	PAPI_LSU_IDL_idx,		 /*Cycles load/store units are idle */
86 //C     	PAPI_TLB_DM_idx,		 /*Data translation lookaside buffer misses */
87 //C     	PAPI_TLB_IM_idx,		 /*Instr translation lookaside buffer misses */
88 //C     	PAPI_TLB_TL_idx,		 /*Total translation lookaside buffer misses */
89 //C     	PAPI_L1_LDM_idx,		 /*Level 1 load misses */
90 //C     	PAPI_L1_STM_idx,		 /*Level 1 store misses */
91 //C     	PAPI_L2_LDM_idx,		 /*Level 2 load misses */
92 //C     	PAPI_L2_STM_idx,		 /*Level 2 store misses */
93 //C     	PAPI_BTAC_M_idx,		 /*BTAC miss */
94 //C     	PAPI_PRF_DM_idx,		 /*Prefetch data instruction caused a miss */
95 //C     	PAPI_L3_DCH_idx,		 /*Level 3 Data Cache Hit */
96 //C     	PAPI_TLB_SD_idx,		 /*Xlation lookaside buffer shootdowns (SMP) */
97 //C     	PAPI_CSR_FAL_idx,		 /*Failed store conditional instructions */
98 /* 0x20 */
99 //C     	PAPI_CSR_SUC_idx,		 /*Successful store conditional instructions */
100 //C     	PAPI_CSR_TOT_idx,		 /*Total store conditional instructions */
101 //C     	PAPI_MEM_SCY_idx,		 /*Cycles Stalled Waiting for Memory Access */
102 //C     	PAPI_MEM_RCY_idx,		 /*Cycles Stalled Waiting for Memory Read */
103 //C     	PAPI_MEM_WCY_idx,		 /*Cycles Stalled Waiting for Memory Write */
104 //C     	PAPI_STL_ICY_idx,		 /*Cycles with No Instruction Issue */
105 //C     	PAPI_FUL_ICY_idx,		 /*Cycles with Maximum Instruction Issue */
106 //C     	PAPI_STL_CCY_idx,		 /*Cycles with No Instruction Completion */
107 //C     	PAPI_FUL_CCY_idx,		 /*Cycles with Maximum Instruction Completion */
108 //C     	PAPI_HW_INT_idx,		 /*Hardware interrupts */
109 //C     	PAPI_BR_UCN_idx,		 /*Unconditional branch instructions executed */
110 //C     	PAPI_BR_CN_idx,			 /*Conditional branch instructions executed */
111 //C     	PAPI_BR_TKN_idx,		 /*Conditional branch instructions taken */
112 //C     	PAPI_BR_NTK_idx,		 /*Conditional branch instructions not taken */
113 //C     	PAPI_BR_MSP_idx,		 /*Conditional branch instructions mispred */
114 //C     	PAPI_BR_PRC_idx,		 /*Conditional branch instructions corr. pred */
115 /* 0x30 */
116 //C     	PAPI_FMA_INS_idx,		 /*FMA instructions completed */
117 //C     	PAPI_TOT_IIS_idx,		 /*Total instructions issued */
118 //C     	PAPI_TOT_INS_idx,		 /*Total instructions executed */
119 //C     	PAPI_INT_INS_idx,		 /*Integer instructions executed */
120 //C     	PAPI_FP_INS_idx,		 /*Floating point instructions executed */
121 //C     	PAPI_LD_INS_idx,		 /*Load instructions executed */
122 //C     	PAPI_SR_INS_idx,		 /*Store instructions executed */
123 //C     	PAPI_BR_INS_idx,		 /*Total branch instructions executed */
124 //C     	PAPI_VEC_INS_idx,		 /*Vector/SIMD instructions executed (could include integer) */
125 //C     	PAPI_RES_STL_idx,		 /*Cycles processor is stalled on resource */
126 //C     	PAPI_FP_STAL_idx,		 /*Cycles any FP units are stalled */
127 //C     	PAPI_TOT_CYC_idx,		 /*Total cycles executed */
128 //C     	PAPI_LST_INS_idx,		 /*Total load/store inst. executed */
129 //C     	PAPI_SYC_INS_idx,		 /*Sync. inst. executed */
130 //C     	PAPI_L1_DCH_idx,		 /*L1 D Cache Hit */
131 //C     	PAPI_L2_DCH_idx,		 /*L2 D Cache Hit */
132 	/* 0x40 */
133 //C     	PAPI_L1_DCA_idx,		 /*L1 D Cache Access */
134 //C     	PAPI_L2_DCA_idx,		 /*L2 D Cache Access */
135 //C     	PAPI_L3_DCA_idx,		 /*L3 D Cache Access */
136 //C     	PAPI_L1_DCR_idx,		 /*L1 D Cache Read */
137 //C     	PAPI_L2_DCR_idx,		 /*L2 D Cache Read */
138 //C     	PAPI_L3_DCR_idx,		 /*L3 D Cache Read */
139 //C     	PAPI_L1_DCW_idx,		 /*L1 D Cache Write */
140 //C     	PAPI_L2_DCW_idx,		 /*L2 D Cache Write */
141 //C     	PAPI_L3_DCW_idx,		 /*L3 D Cache Write */
142 //C     	PAPI_L1_ICH_idx,		 /*L1 instruction cache hits */
143 //C     	PAPI_L2_ICH_idx,		 /*L2 instruction cache hits */
144 //C     	PAPI_L3_ICH_idx,		 /*L3 instruction cache hits */
145 //C     	PAPI_L1_ICA_idx,		 /*L1 instruction cache accesses */
146 //C     	PAPI_L2_ICA_idx,		 /*L2 instruction cache accesses */
147 //C     	PAPI_L3_ICA_idx,		 /*L3 instruction cache accesses */
148 //C     	PAPI_L1_ICR_idx,		 /*L1 instruction cache reads */
149 	/* 0x50 */
150 //C     	PAPI_L2_ICR_idx,		 /*L2 instruction cache reads */
151 //C     	PAPI_L3_ICR_idx,		 /*L3 instruction cache reads */
152 //C     	PAPI_L1_ICW_idx,		 /*L1 instruction cache writes */
153 //C     	PAPI_L2_ICW_idx,		 /*L2 instruction cache writes */
154 //C     	PAPI_L3_ICW_idx,		 /*L3 instruction cache writes */
155 //C     	PAPI_L1_TCH_idx,		 /*L1 total cache hits */
156 //C     	PAPI_L2_TCH_idx,		 /*L2 total cache hits */
157 //C     	PAPI_L3_TCH_idx,		 /*L3 total cache hits */
158 //C     	PAPI_L1_TCA_idx,		 /*L1 total cache accesses */
159 //C     	PAPI_L2_TCA_idx,		 /*L2 total cache accesses */
160 //C     	PAPI_L3_TCA_idx,		 /*L3 total cache accesses */
161 //C     	PAPI_L1_TCR_idx,		 /*L1 total cache reads */
162 //C     	PAPI_L2_TCR_idx,		 /*L2 total cache reads */
163 //C     	PAPI_L3_TCR_idx,		 /*L3 total cache reads */
164 //C     	PAPI_L1_TCW_idx,		 /*L1 total cache writes */
165 //C     	PAPI_L2_TCW_idx,		 /*L2 total cache writes */
166 	/* 0x60 */
167 //C     	PAPI_L3_TCW_idx,		 /*L3 total cache writes */
168 //C     	PAPI_FML_INS_idx,		 /*FM ins */
169 //C     	PAPI_FAD_INS_idx,		 /*FA ins */
170 //C     	PAPI_FDV_INS_idx,		 /*FD ins */
171 //C     	PAPI_FSQ_INS_idx,		 /*FSq ins */
172 //C     	PAPI_FNV_INS_idx,		 /*Finv ins */
173 //C     	PAPI_FP_OPS_idx,		 /*Floating point operations executed */
174 //C     	PAPI_SP_OPS_idx,		 /* Floating point operations executed; optimized to count scaled single precision vector operations */
175 //C     	PAPI_DP_OPS_idx,		 /* Floating point operations executed; optimized to count scaled double precision vector operations */
176 //C     	PAPI_VEC_SP_idx,		 /* Single precision vector/SIMD instructions */
177 //C     	PAPI_VEC_DP_idx,		 /* Double precision vector/SIMD instructions */
178 //C     	PAPI_REF_CYC_idx,		 /* Reference clock cycles */
179 //C     	PAPI_END_idx			 /*This should always be last! */
180 //C     };
181 enum
182 {
183     PAPI_L1_DCM_idx,
184     PAPI_L1_ICM_idx,
185     PAPI_L2_DCM_idx,
186     PAPI_L2_ICM_idx,
187     PAPI_L3_DCM_idx,
188     PAPI_L3_ICM_idx,
189     PAPI_L1_TCM_idx,
190     PAPI_L2_TCM_idx,
191     PAPI_L3_TCM_idx,
192     PAPI_CA_SNP_idx,
193     PAPI_CA_SHR_idx,
194     PAPI_CA_CLN_idx,
195     PAPI_CA_INV_idx,
196     PAPI_CA_ITV_idx,
197     PAPI_L3_LDM_idx,
198     PAPI_L3_STM_idx,
199     PAPI_BRU_IDL_idx,
200     PAPI_FXU_IDL_idx,
201     PAPI_FPU_IDL_idx,
202     PAPI_LSU_IDL_idx,
203     PAPI_TLB_DM_idx,
204     PAPI_TLB_IM_idx,
205     PAPI_TLB_TL_idx,
206     PAPI_L1_LDM_idx,
207     PAPI_L1_STM_idx,
208     PAPI_L2_LDM_idx,
209     PAPI_L2_STM_idx,
210     PAPI_BTAC_M_idx,
211     PAPI_PRF_DM_idx,
212     PAPI_L3_DCH_idx,
213     PAPI_TLB_SD_idx,
214     PAPI_CSR_FAL_idx,
215     PAPI_CSR_SUC_idx,
216     PAPI_CSR_TOT_idx,
217     PAPI_MEM_SCY_idx,
218     PAPI_MEM_RCY_idx,
219     PAPI_MEM_WCY_idx,
220     PAPI_STL_ICY_idx,
221     PAPI_FUL_ICY_idx,
222     PAPI_STL_CCY_idx,
223     PAPI_FUL_CCY_idx,
224     PAPI_HW_INT_idx,
225     PAPI_BR_UCN_idx,
226     PAPI_BR_CN_idx,
227     PAPI_BR_TKN_idx,
228     PAPI_BR_NTK_idx,
229     PAPI_BR_MSP_idx,
230     PAPI_BR_PRC_idx,
231     PAPI_FMA_INS_idx,
232     PAPI_TOT_IIS_idx,
233     PAPI_TOT_INS_idx,
234     PAPI_INT_INS_idx,
235     PAPI_FP_INS_idx,
236     PAPI_LD_INS_idx,
237     PAPI_SR_INS_idx,
238     PAPI_BR_INS_idx,
239     PAPI_VEC_INS_idx,
240     PAPI_RES_STL_idx,
241     PAPI_FP_STAL_idx,
242     PAPI_TOT_CYC_idx,
243     PAPI_LST_INS_idx,
244     PAPI_SYC_INS_idx,
245     PAPI_L1_DCH_idx,
246     PAPI_L2_DCH_idx,
247     PAPI_L1_DCA_idx,
248     PAPI_L2_DCA_idx,
249     PAPI_L3_DCA_idx,
250     PAPI_L1_DCR_idx,
251     PAPI_L2_DCR_idx,
252     PAPI_L3_DCR_idx,
253     PAPI_L1_DCW_idx,
254     PAPI_L2_DCW_idx,
255     PAPI_L3_DCW_idx,
256     PAPI_L1_ICH_idx,
257     PAPI_L2_ICH_idx,
258     PAPI_L3_ICH_idx,
259     PAPI_L1_ICA_idx,
260     PAPI_L2_ICA_idx,
261     PAPI_L3_ICA_idx,
262     PAPI_L1_ICR_idx,
263     PAPI_L2_ICR_idx,
264     PAPI_L3_ICR_idx,
265     PAPI_L1_ICW_idx,
266     PAPI_L2_ICW_idx,
267     PAPI_L3_ICW_idx,
268     PAPI_L1_TCH_idx,
269     PAPI_L2_TCH_idx,
270     PAPI_L3_TCH_idx,
271     PAPI_L1_TCA_idx,
272     PAPI_L2_TCA_idx,
273     PAPI_L3_TCA_idx,
274     PAPI_L1_TCR_idx,
275     PAPI_L2_TCR_idx,
276     PAPI_L3_TCR_idx,
277     PAPI_L1_TCW_idx,
278     PAPI_L2_TCW_idx,
279     PAPI_L3_TCW_idx,
280     PAPI_FML_INS_idx,
281     PAPI_FAD_INS_idx,
282     PAPI_FDV_INS_idx,
283     PAPI_FSQ_INS_idx,
284     PAPI_FNV_INS_idx,
285     PAPI_FP_OPS_idx,
286     PAPI_SP_OPS_idx,
287     PAPI_DP_OPS_idx,
288     PAPI_VEC_SP_idx,
289     PAPI_VEC_DP_idx,
290     PAPI_REF_CYC_idx,
291     PAPI_END_idx,
292 }
293 
294 const  PAPI_L1_DCM = (PAPI_L1_DCM_idx  | PAPI_PRESET_MASK)	/*Level 1 data cache misses */
295 const  PAPI_L1_ICM = (PAPI_L1_ICM_idx  | PAPI_PRESET_MASK)	;/*Level 1 instruction cache misses */
296 const  PAPI_L2_DCM = (PAPI_L2_DCM_idx  | PAPI_PRESET_MASK)	;/*Level 2 data cache misses */
297 const  PAPI_L2_ICM = (PAPI_L2_ICM_idx  | PAPI_PRESET_MASK)	;/*Level 2 instruction cache misses */
298 const  PAPI_L3_DCM = (PAPI_L3_DCM_idx  | PAPI_PRESET_MASK)	;/*Level 3 data cache misses */
299 const  PAPI_L3_ICM = (PAPI_L3_ICM_idx  | PAPI_PRESET_MASK)	;/*Level 3 instruction cache misses */
300 const  PAPI_L1_TCM = (PAPI_L1_TCM_idx  | PAPI_PRESET_MASK)	;/*Level 1 total cache misses */
301 const  PAPI_L2_TCM = (PAPI_L2_TCM_idx  | PAPI_PRESET_MASK)	;/*Level 2 total cache misses */
302 const  PAPI_L3_TCM = (PAPI_L3_TCM_idx  | PAPI_PRESET_MASK)	;/*Level 3 total cache misses */
303 const  PAPI_CA_SNP = (PAPI_CA_SNP_idx  | PAPI_PRESET_MASK)	;/*Snoops */
304 const  PAPI_CA_SHR = (PAPI_CA_SHR_idx  | PAPI_PRESET_MASK)	;/*Request for shared cache line (SMP) */
305 const  PAPI_CA_CLN = (PAPI_CA_CLN_idx  | PAPI_PRESET_MASK)	;/*Request for clean cache line (SMP) */
306 const  PAPI_CA_INV = (PAPI_CA_INV_idx  | PAPI_PRESET_MASK)	;/*Request for cache line Invalidation (SMP) */
307 const  PAPI_CA_ITV = (PAPI_CA_ITV_idx  | PAPI_PRESET_MASK)	;/*Request for cache line Intervention (SMP) */
308 const  PAPI_L3_LDM = (PAPI_L3_LDM_idx  | PAPI_PRESET_MASK)	;/*Level 3 load misses */
309 const  PAPI_L3_STM = (PAPI_L3_STM_idx  | PAPI_PRESET_MASK)	;/*Level 3 store misses */
310 const  PAPI_BRU_IDL= (PAPI_BRU_IDL_idx | PAPI_PRESET_MASK)	;/*Cycles branch units are idle */
311 const  PAPI_FXU_IDL= (PAPI_FXU_IDL_idx | PAPI_PRESET_MASK)	;/*Cycles integer units are idle */
312 const  PAPI_FPU_IDL= (PAPI_FPU_IDL_idx | PAPI_PRESET_MASK)	;/*Cycles floating point units are idle */
313 const  PAPI_LSU_IDL= (PAPI_LSU_IDL_idx | PAPI_PRESET_MASK)	;/*Cycles load/store units are idle */
314 const  PAPI_TLB_DM = (PAPI_TLB_DM_idx  | PAPI_PRESET_MASK)	;/*Data translation lookaside buffer misses */
315 const  PAPI_TLB_IM = (PAPI_TLB_IM_idx  | PAPI_PRESET_MASK)	;/*Instr translation lookaside buffer misses */
316 const  PAPI_TLB_TL = (PAPI_TLB_TL_idx  | PAPI_PRESET_MASK)	;/*Total translation lookaside buffer misses */
317 const  PAPI_L1_LDM = (PAPI_L1_LDM_idx  | PAPI_PRESET_MASK)	;/*Level 1 load misses */
318 const  PAPI_L1_STM = (PAPI_L1_STM_idx  | PAPI_PRESET_MASK)	;/*Level 1 store misses */
319 const  PAPI_L2_LDM = (PAPI_L2_LDM_idx  | PAPI_PRESET_MASK)	;/*Level 2 load misses */
320 const  PAPI_L2_STM = (PAPI_L2_STM_idx  | PAPI_PRESET_MASK)	;/*Level 2 store misses */
321 const  PAPI_BTAC_M = (PAPI_BTAC_M_idx  | PAPI_PRESET_MASK)	;/*BTAC miss */
322 const  PAPI_PRF_DM = (PAPI_PRF_DM_idx  | PAPI_PRESET_MASK)	;/*Prefetch data instruction caused a miss */
323 const  PAPI_L3_DCH = (PAPI_L3_DCH_idx  | PAPI_PRESET_MASK)	;/*Level 3 Data Cache Hit */
324 const  PAPI_TLB_SD = (PAPI_TLB_SD_idx  | PAPI_PRESET_MASK)	;/*Xlation lookaside buffer shootdowns (SMP) */
325 const  PAPI_CSR_FAL= (PAPI_CSR_FAL_idx | PAPI_PRESET_MASK)	;/*Failed store conditional instructions */
326 const  PAPI_CSR_SUC= (PAPI_CSR_SUC_idx | PAPI_PRESET_MASK)	;/*Successful store conditional instructions */
327 const  PAPI_CSR_TOT= (PAPI_CSR_TOT_idx | PAPI_PRESET_MASK)	;/*Total store conditional instructions */
328 const  PAPI_MEM_SCY= (PAPI_MEM_SCY_idx | PAPI_PRESET_MASK)	;/*Cycles Stalled Waiting for Memory Access */
329 const  PAPI_MEM_RCY= (PAPI_MEM_RCY_idx | PAPI_PRESET_MASK)	;/*Cycles Stalled Waiting for Memory Read */
330 const  PAPI_MEM_WCY= (PAPI_MEM_WCY_idx | PAPI_PRESET_MASK)	;/*Cycles Stalled Waiting for Memory Write */
331 const  PAPI_STL_ICY= (PAPI_STL_ICY_idx | PAPI_PRESET_MASK)	;/*Cycles with No Instruction Issue */
332 const  PAPI_FUL_ICY= (PAPI_FUL_ICY_idx | PAPI_PRESET_MASK)	;/*Cycles with Maximum Instruction Issue */
333 const  PAPI_STL_CCY= (PAPI_STL_CCY_idx | PAPI_PRESET_MASK)	;/*Cycles with No Instruction Completion */
334 const  PAPI_FUL_CCY= (PAPI_FUL_CCY_idx | PAPI_PRESET_MASK)	;/*Cycles with Maximum Instruction Completion */
335 const  PAPI_HW_INT = (PAPI_HW_INT_idx  | PAPI_PRESET_MASK)	;/*Hardware interrupts */
336 const  PAPI_BR_UCN = (PAPI_BR_UCN_idx  | PAPI_PRESET_MASK)	;/*Unconditional branch instructions executed */
337 const  PAPI_BR_CN  = (PAPI_BR_CN_idx   | PAPI_PRESET_MASK)	;/*Conditional branch instructions executed */
338 const  PAPI_BR_TKN = (PAPI_BR_TKN_idx  | PAPI_PRESET_MASK)	;/*Conditional branch instructions taken */
339 const  PAPI_BR_NTK = (PAPI_BR_NTK_idx  | PAPI_PRESET_MASK)	;/*Conditional branch instructions not taken */
340 const  PAPI_BR_MSP = (PAPI_BR_MSP_idx  | PAPI_PRESET_MASK)	;/*Conditional branch instructions mispred */
341 const  PAPI_BR_PRC = (PAPI_BR_PRC_idx  | PAPI_PRESET_MASK)	;/*Conditional branch instructions corr. pred */
342 const  PAPI_FMA_INS= (PAPI_FMA_INS_idx | PAPI_PRESET_MASK)	;/*FMA instructions completed */
343 const  PAPI_TOT_IIS= (PAPI_TOT_IIS_idx | PAPI_PRESET_MASK)	;/*Total instructions issued */
344 const  PAPI_TOT_INS= (PAPI_TOT_INS_idx | PAPI_PRESET_MASK)	;/*Total instructions executed */
345 const  PAPI_INT_INS= (PAPI_INT_INS_idx | PAPI_PRESET_MASK)	;/*Integer instructions executed */
346 const  PAPI_FP_INS = (PAPI_FP_INS_idx  | PAPI_PRESET_MASK)	;/*Floating point instructions executed */
347 const  PAPI_LD_INS = (PAPI_LD_INS_idx  | PAPI_PRESET_MASK)	;/*Load instructions executed */
348 const  PAPI_SR_INS = (PAPI_SR_INS_idx  | PAPI_PRESET_MASK)	;/*Store instructions executed */
349 const  PAPI_BR_INS = (PAPI_BR_INS_idx  | PAPI_PRESET_MASK)	;/*Total branch instructions executed */
350 const  PAPI_VEC_INS= (PAPI_VEC_INS_idx | PAPI_PRESET_MASK)	;/*Vector/SIMD instructions executed (could include integer) */
351 const  PAPI_RES_STL= (PAPI_RES_STL_idx | PAPI_PRESET_MASK)	;/*Cycles processor is stalled on resource */
352 const  PAPI_FP_STAL= (PAPI_FP_STAL_idx | PAPI_PRESET_MASK)	;/*Cycles any FP units are stalled */
353 const  PAPI_TOT_CYC= (PAPI_TOT_CYC_idx | PAPI_PRESET_MASK)	;/*Total cycles executed */
354 const  PAPI_LST_INS= (PAPI_LST_INS_idx | PAPI_PRESET_MASK)	;/*Total load/store inst. executed */
355 const  PAPI_SYC_INS= (PAPI_SYC_INS_idx | PAPI_PRESET_MASK)	;/*Sync. inst. executed */
356 const  PAPI_L1_DCH = (PAPI_L1_DCH_idx  | PAPI_PRESET_MASK)	;/*L1 D Cache Hit */
357 const  PAPI_L2_DCH = (PAPI_L2_DCH_idx  | PAPI_PRESET_MASK)	;/*L2 D Cache Hit */
358 const  PAPI_L1_DCA = (PAPI_L1_DCA_idx  | PAPI_PRESET_MASK)	;/*L1 D Cache Access */
359 const  PAPI_L2_DCA = (PAPI_L2_DCA_idx  | PAPI_PRESET_MASK)	;/*L2 D Cache Access */
360 const  PAPI_L3_DCA = (PAPI_L3_DCA_idx  | PAPI_PRESET_MASK)	;/*L3 D Cache Access */
361 const  PAPI_L1_DCR = (PAPI_L1_DCR_idx  | PAPI_PRESET_MASK)	;/*L1 D Cache Read */
362 const  PAPI_L2_DCR = (PAPI_L2_DCR_idx  | PAPI_PRESET_MASK)	;/*L2 D Cache Read */
363 const  PAPI_L3_DCR = (PAPI_L3_DCR_idx  | PAPI_PRESET_MASK)	;/*L3 D Cache Read */
364 const  PAPI_L1_DCW = (PAPI_L1_DCW_idx  | PAPI_PRESET_MASK)	;/*L1 D Cache Write */
365 const  PAPI_L2_DCW = (PAPI_L2_DCW_idx  | PAPI_PRESET_MASK)	;/*L2 D Cache Write */
366 const  PAPI_L3_DCW = (PAPI_L3_DCW_idx  | PAPI_PRESET_MASK)	;/*L3 D Cache Write */
367 const  PAPI_L1_ICH = (PAPI_L1_ICH_idx  | PAPI_PRESET_MASK)	;/*L1 instruction cache hits */
368 const  PAPI_L2_ICH = (PAPI_L2_ICH_idx  | PAPI_PRESET_MASK)	;/*L2 instruction cache hits */
369 const  PAPI_L3_ICH = (PAPI_L3_ICH_idx  | PAPI_PRESET_MASK)	;/*L3 instruction cache hits */
370 const  PAPI_L1_ICA = (PAPI_L1_ICA_idx  | PAPI_PRESET_MASK)	;/*L1 instruction cache accesses */
371 const  PAPI_L2_ICA = (PAPI_L2_ICA_idx  | PAPI_PRESET_MASK)	;/*L2 instruction cache accesses */
372 const  PAPI_L3_ICA = (PAPI_L3_ICA_idx  | PAPI_PRESET_MASK)	;/*L3 instruction cache accesses */
373 const  PAPI_L1_ICR = (PAPI_L1_ICR_idx  | PAPI_PRESET_MASK)	;/*L1 instruction cache reads */
374 const  PAPI_L2_ICR = (PAPI_L2_ICR_idx  | PAPI_PRESET_MASK)	;/*L2 instruction cache reads */
375 const  PAPI_L3_ICR = (PAPI_L3_ICR_idx  | PAPI_PRESET_MASK)	;/*L3 instruction cache reads */
376 const  PAPI_L1_ICW = (PAPI_L1_ICW_idx  | PAPI_PRESET_MASK)	;/*L1 instruction cache writes */
377 const  PAPI_L2_ICW = (PAPI_L2_ICW_idx  | PAPI_PRESET_MASK)	;/*L2 instruction cache writes */
378 const  PAPI_L3_ICW = (PAPI_L3_ICW_idx  | PAPI_PRESET_MASK)	;/*L3 instruction cache writes */
379 const  PAPI_L1_TCH = (PAPI_L1_TCH_idx  | PAPI_PRESET_MASK)	;/*L1 total cache hits */
380 const  PAPI_L2_TCH = (PAPI_L2_TCH_idx  | PAPI_PRESET_MASK)	;/*L2 total cache hits */
381 const  PAPI_L3_TCH = (PAPI_L3_TCH_idx  | PAPI_PRESET_MASK)	;/*L3 total cache hits */
382 const  PAPI_L1_TCA = (PAPI_L1_TCA_idx  | PAPI_PRESET_MASK)	;/*L1 total cache accesses */
383 const  PAPI_L2_TCA = (PAPI_L2_TCA_idx  | PAPI_PRESET_MASK)	;/*L2 total cache accesses */
384 const  PAPI_L3_TCA = (PAPI_L3_TCA_idx  | PAPI_PRESET_MASK)	;/*L3 total cache accesses */
385 const  PAPI_L1_TCR = (PAPI_L1_TCR_idx  | PAPI_PRESET_MASK)	;/*L1 total cache reads */
386 const  PAPI_L2_TCR = (PAPI_L2_TCR_idx  | PAPI_PRESET_MASK)	;/*L2 total cache reads */
387 const  PAPI_L3_TCR = (PAPI_L3_TCR_idx  | PAPI_PRESET_MASK)	;/*L3 total cache reads */
388 const  PAPI_L1_TCW = (PAPI_L1_TCW_idx  | PAPI_PRESET_MASK)	;/*L1 total cache writes */
389 const  PAPI_L2_TCW = (PAPI_L2_TCW_idx  | PAPI_PRESET_MASK)	;/*L2 total cache writes */
390 const  PAPI_L3_TCW = (PAPI_L3_TCW_idx  | PAPI_PRESET_MASK)	;/*L3 total cache writes */
391 const  PAPI_FML_INS= (PAPI_FML_INS_idx | PAPI_PRESET_MASK)	;/*FM ins */
392 const  PAPI_FAD_INS= (PAPI_FAD_INS_idx | PAPI_PRESET_MASK)	;/*FA ins */
393 const  PAPI_FDV_INS= (PAPI_FDV_INS_idx | PAPI_PRESET_MASK)	;/*FD ins */
394 const  PAPI_FSQ_INS= (PAPI_FSQ_INS_idx | PAPI_PRESET_MASK)	;/*FSq ins */
395 const  PAPI_FNV_INS= (PAPI_FNV_INS_idx | PAPI_PRESET_MASK)	;/*Finv ins */
396 const  PAPI_FP_OPS = (PAPI_FP_OPS_idx  | PAPI_PRESET_MASK)	;/*Floating point operations executed */
397 const  PAPI_SP_OPS = (PAPI_SP_OPS_idx  | PAPI_PRESET_MASK)	;/* Floating point operations executed; optimized to count scaled single precision vector operations */
398 const  PAPI_DP_OPS = (PAPI_DP_OPS_idx  | PAPI_PRESET_MASK)	;/* Floating point operations executed; optimized to count scaled double precision vector operations */
399 const  PAPI_VEC_SP = (PAPI_VEC_SP_idx  | PAPI_PRESET_MASK)	;/* Single precision vector/SIMD instructions */
400 const  PAPI_VEC_DP = (PAPI_VEC_DP_idx  | PAPI_PRESET_MASK)	;/* Double precision vector/SIMD instructions */
401 const  PAPI_REF_CYC= (PAPI_REF_CYC_idx  | PAPI_PRESET_MASK);	/* Reference cconst */
402 const  PAPI_END    = (PAPI_END_idx  | PAPI_PRESET_MASK);	/*T;his should always be last! */
403 
404 //C     #endif
405